Conference Theme: Integrated Circuits and Systems for the Connection of Intelligent Things
The impact of COVID-19 has accelerated the trend of the mobile connectivity. Remote working, video conferencing, and contactless business markets are booming via the link of billions of smart devices. Unrelenting innovations of solid-state circuits and systems have brought powerful communication vehicles into mobile form factors. Thereby, the role of integrated circuits has been more critical than ever to build an intelligent connection between human and human with high security and low power. A-SSCC 2021 is looking for innovative silicon systems and circuit solutions to enrich our life with the Connection of Intelligent Things.
The IEEE A-SSCC 2021 (Asian Solid-State Circuits Conference) is an international forum for presenting the most updated and advanced chips and
circuit designs in solid-state and semiconductor fields. The conference is supported by the IEEE Solid-State Circuits Society and will be held in
Asia. Further details on the conference and paper submission guidelines and templates are available at the A-SSCC official website:
Prospective authors are invited to submit a paper based on the template shown in the official A-SSCC 2021 website, which is a two-page manuscript plus an optional one-page supplementary figures. Supplementary figures should not be referred to in the text of the two-page manuscript. For further details, see the A-SSCC Website. Papers are solicited in the following categories:
- 1. Analog Circuits & Systems
Amplifiers, comparators, switched capacitor circuits, continuous-time & discrete-time filters, voltage/current references; DC-DC converters, power-control circuits; IF/baseband analog circuits, AGC/VGA; non-linear analog circuits.
- 2. Data Converters
Nyquist-rate and oversampling A/D, D/A converters, time-to-digital converters, and capacitance-to-digital converters; sub-circuits for data converters including sample-and-hold circuits, calibration circuits, etc.
- 3. Digital Circuits & Systems
Design, fabrication, and test of digital VLSI systems; high-speed low-power digital circuits, power-reduction and management methods for digital VLSI, ultra-low-voltage and sub-threshold logic design; leakage reduction techniques; clock distribution, I/O circuits, reconfigurable logicarray circuits; supply/substrate noise measurement and cancellation for digital VLSI, variation and fault-tolerant circuits.
- 4. SoC & Signal Processing Systems
System-on-chip (including 3D integration), microprocessors, network processors, baseband communication processing system & architectures, system-level power management; multimedia and recognition processing systems; cryptographic, security, machine learning, deep-learning, and neuromorphic circuits and systems; bio-medical/neural-network processors and sensor network systems.
- 5. Wireless
Receivers/transmitters/transceivers for wireless systems; narrowband RF, ultra-wideband and millimeter-wave circuits; circuits and building-blocks including RF front-end, LNA, mixer, power amplifiers, VCOs, frequency synthesizers, RF filters, RF switches, power detectors, active antennas.
- 6. Wireline
Receivers/transmitters/transceivers for wireline systems; optical/electrical data links and backplane transceivers; power-line communication; clock generation circuits, PLL, DLL, spread-spectrum clock generation; building blocks for high-speed wireline communication; analog-digital mixed-mode circuits.
- 7. Emerging Technologies and Applications
Advanced system designs and circuit solutions for technologies and applications including state-of-the-art devices and packaging technologies; flexible and printable electronics; silicon photonics; smart sensors and transducers; MEMS for analog, RF, and sensor applications; image sensors and displays; energy harvesting systems; transceiver systems; medical/bio-electronics/bio-inspired chip design, artificial intelligent system, and cryogenic circuits and systems.
- 8. Memory
Volatile and Non-volatile memory; new memory designs for 3D/2D architectures, emerging devices such as resistive-/phase change-/magnetic- /ferroelectric- memory devices; data storage and multi-bit-cell memory design; cache-memory system, multi-port memory, memory subsystem, processing in memory, and CAM design; yield-enhancing and ECC techniques; memory testing and built-in self-test.
- 9. FPGA
Novel algorithm and/or architecture for integrated circuits validated by FPGA implementation. The authors of accepted papers are required to participate in demo sessions.
- 1. Industry Program
This special category accepts only papers based on state-of-the-art industrial products. Strong emphasis on systems realized by silicon chips is encouraged. The papers should cover architecture, circuits, process technology, packaging and testing, including characterization results, die and system photos, as well as product demos.
- 2. Demonstration Program
Three demonstration sessions will be held during the Conference. Student Design Contest (SDC) and FPGA Demo will be presented by the authors of selected papers, and Industry Demo will be offered by industry groups who voluntarily apply for participation without paper submission.
- 3. Special Programs
Diverse special programs including Educational Session, Panels, and Forums will be organized. In addition, other exciting special programs such as joint session, mentoring session, and workshops will be held during the Conference.
Papers related to integrated circuits for intelligent systems are highly solicited. Papers on low-power and/or low-voltage approaches, signal integrity, noise, test, and manufacturability for all the above categories are welcomed. Measurement results are highly recommended, especially for analog, and RF categories. Design methodologies for SiP, and SoC are included in the scope of the conference; the papers only describing CAD tools and CAD algorithms are not considered. Authors must follow detailed instructions provided within the “Authors” section of the website, including the Authors’ Guide and Pre-Publication Policy. The technical content beyond the abstract of the accepted paper must not be announced, published, or in any way put in the public domain prior to the Conference. Extended versions of selected papers from |the Conference will be published in a Special Issue of the IEEE Journal of Solid-State Circuits and a Special Issue of the IEEE Solid-State Circuits Letters.
June 7, 2021, 20:00 (GMT)June 21, 2021, 23:59 (GMT -07:00)
- Acceptance notification August 2, 2021
- Final paper submission September 3, 2021
||Hoi-Jun Yoo, KAIST, Korea
||Chair ES Jung, Samsung Electronics, Korea
|Organizing Committee Chair
||Yong Moon, Soongsil University, Korea
|Organizing Committee Vice-Chair
||Taewook Kim, Yonsei University, Korea
|Technical Program Committee
||Woogeun Rhee, Tsinghua University, China
||SeongHwan Cho, KAIST, Korea
||Shouyi Yin, Tsinghua University, China