Date : Nov. 8, 2021
Time : 16:00-17:40 (Korea Standard Time)
PIM (Processing in Memory) will go with Analog or Digital?
The unprecedented growth in computing and processing has led to massive amounts of data movement from off-chip units to on-chip memories. To deal with the complex processing, shall we use analog circuits or digital circuits? If digital, what are the popular techniques and the main bottleneck? If analog, what are the emerging solutions and the design challenges? In this panel discussion session, we will have 6-7 experts as the panelists to share their view.
Zhihua Wang, Tsinghua University, China
Bo Zhao, Zhejiang University, China
Seung-Tak Ryu, KAIST, South Korea
Bo Zhao, Zhejiang University, China
Feng Lin (Changxin Memory Technology) / Will industries embrace processing-in-memory (PIM)? And How?
Tony T. Kim (Nanyang Technological University) / Will nonvolatile memories help to improve the efficiency of PIM?
Ken Takeuchi (University of Tokyo) / How to heterogeneously integrate PIM for Edge AI?
Yuchao Yang (Peking University, China) / How to conduct PIM through memristors?
Bin Gao (Tsinghua University, China) / What’s the design challenges in analog RRAM for PIM?
Will industries embrace processing-in-memory (PIM)? And How?
Feng LinChangxin Memory TechnologyFeng Lin received his Ph.D. in Electrical Engineering from University of Idaho, United States in 2000, and MSEE and BSEE degrees from University of Electronics, Science and Technology of China in 1995 and 1992 respectively. From 2000 to 2019, Dr. Lin was with Micron Technology, Inc. in Boise, Idaho, as a Senior Member of Technical Staff, developing industry leading memory products, including GDDR6x, Hybrid-memory cube (HMC), and various low-power and high-speed memory interfaces. Dr. Lin holds over 120 US and international patents and is a co-author of textbook DRAM Circuit Design, Fundamental and High-Speed Topics(IEEE Press 2007). Since 2019, Dr. Lin isa Fellow in Product R&D departmentat Changxin Memory Technologies, Inc.,overseeingtechnologydevelopment of advancedmemory products.His research interests include high-speed energy efficient I/O, signal & power integrity, advanced memory architecture and memoryapplications in AI and datacenters.AI (artificial intelligent) and ML (machine learning) bring computing into data centric world. Conventional Von-Neumann architecture creates big bottleneck for data movement between CPU and off-chip memory, which results in limited bandwidth, longer latency and wasted energy. Processing-in-memory (PIM) has been brought up to break the memory wall and combinedata storage and compute in one place. The concept is not new, but it hardly finds its place in the industry, especially for DRAM-based approach. Asgeneral-purpose DRAM getsbigger and faster, there is still needs to exploring PIM for some special applications and maximize overall performance per watts. This talk will give a few examples for real PIM implementations in the industry, their pros and cons, and discuss potential solutions to make it a reality in the memory industry.
Will nonvolatile memories help to improve the efficiency of PIM?
Tony T. KimNanyang Technological UniversityProf. Tony Tae-Hyoung Kim received the B.S. and M.S. degrees in electrical engineering from Korea University, Seoul, Korea, in 1999 and 2001, respectively. He received the Ph.D. degree in electrical and computer engineering from the University of Minnesota, Minneapolis, MN, USA in 2009. From 2001 to 2005, he worked for Samsung Electronics. In November 2009, he joined Nanyang Technological University where he is currently an associate professor. His current research interests include in-memory computing for edge computing, emerging memory circuit design, energy-efficient circuits and systems for IoT and wearable devices, and variation tolerant circuits and systems.
He has received many awards including Best Demo Award at 2016 IEEE APCCAS, International Low Power Design Contest award at 2016 IEEE/ACM ISLPED, etc. He is an author/co-author of +190 journal and conference papers and holds 17 US and Korean patents. He was the Chair of IEEE SSCS Singapore Chapter in 2015~2016. He is the Chair-Elect/Secretary of IEEE CASS VLSI Systems & Applications Technical Committee and a senior member of IEEE.Which nonvolatile memories are more promising? What are the challenges in nonvolatile PIM design? What are the pros and cons of nonvolatile PIM? What are the target applications of nonvolatile PIM? Can nonvolatile PIM provide satisfactory accuracy?
How to heterogeneously integrate PIM for Edge AI?
Ken TakeuchiUniversity of TokyoKen Takeuchi is currently a Professor at Department of Electrical Engineering and Information Systems, Graduate School of Engineering of The University of Tokyo. He is now working on data-centric computing such as computation in memory, approximate computing, data scale computing, AI chip design and brain-inspired memory. He received the B.S. and M.S. degrees in Applied Physics and the Ph.D. degree in Electric Engineering from The University of Tokyo in 1991, 1993 and 2006, respectively. In 2003, he also received the M.B.A. degree from Stanford University. He has authored numerous technical papers, one of which won the Takuo Sugano Award for Outstanding Paper at ISSCC 2007. He served as the symposium chair of Symposium on VLSI Circuits 2021. He has also served on the program committee member of International Solid-State Circuits Conference (ISSCC), Custom Integrated Circuits Conference (CICC), Asian Solid-State Circuits Conference (A-SSCC), International Memory Workshop (IMW) and International Conference on Solid State Devices and Materials (SSDM).By the thermal limit, the frequency of general CPU is hitting the ceiling. Thus, domain specific computing with dedicated accelerators like PIM is required especially for emerging AI applications. This talk discusses how to heterogeneously integrate traditional CPU and PIM for edge AI applications. Software support such as programming model & compiler is essential. Moreover, co-design of algorithm, circuit & device becomes KEY. In addition, to achieve a massively parallel MAC (Multiply-Accumulate) operation, voltage sensing vs. current sensing of PIM is discussed.
How to conduct PIM through memristors?
Yuchao YangPeking University, ChinaYuchao Yang serves as Director of Center for Brain Inspired Chips at Peking University and Executive Director of Center for Brain Inspired Intelligence at Chinese Institute for Brain Science. His research interests include memristors, neuromorphic computing, and in-memory computing. He has published over 100 papers in high-profile journals and conferences such as Nature Electronics, Nature Communications, Nature Nanotechnology, Science Advances, Advanced Materials, Nano Letters, IEDM, etc. as well as 5 book chapters. His papers have been cited >5500 times, with an H-index of 33. He was invited to give >30 keynote/invited talks on international conferences and serves as TPC chair or member for 9 international conferences. Yuchao Yang serves as the Associate Editor for Nano Select and editorial board member of Chip, Scientific Reports and Science China Information Sciences. He was invited to guest edit 3 special issues and write 12 News & Views, review articles, etc. He is a member of IEEE, MRS and RSC. He is a recipient of the National Outstanding Youth Science Fund, Qiu Shi Outstanding Young Scholar Award, Wiley Young Researcher Award, MIT Technology Review Innovators Under 35 in China, and the EXPLORER PRIZE.Since the connection of the theoretical memristor concept with physical resistive switching devices in 2008, tremendous progress has been made in terms of material and device technology developments and their applications in memory and computing systems. The physical embodiments of memristors correspond to various resistive switching devices based on different mechanisms. These mechanisms endow the memristors with rich nonlinear dynamics, which is key to constructing biologically plausible dynamic computing systems. Memristor can be described as a set of differential equations that indicate how the internal state variables determine device characteristics and how external electrical stimulations influence these state variables. The increases in the number of state variables and internal dynamics have dramatically enriched the dynamics and functionality of memristors. Further exploration and control of such dynamics are essential for highly efficient information processing applications.
What’s the design challenges in analog RRAM for PIM?
Bin GaoTsinghua University, ChinaBin Gao is currently an Associate Professor with the School of Integrated Circuits, Tsinghua University, Beijing, China. He received the B.S. degree in 2008 and Ph.D. degree in 2013, both from Peking University, Beijing, China. His current research interests include fabrication, characterization, and modeling of emerging semiconductor devices, especially RRAM, and design of computation-in-memory and neuro-inspired computing system. He has published more than 100 technical papers on Nature, Nature Electronics, Proceedings of the IEEE, EDL, TED, JSSC, IEDM, ISSCC, VLSI, etc. His total citation is over 6000. He was a recipient of the IEEE EDS Ph.D. Student Fellowship in 2012. He served as Sub-committee Chair of IEDM, EDTM, and ICTA, and TPC member of DAC, IRPS, IPFA, etc.Resistive Random Access Memory (RRAM) technology provides great opportunity for implementation of Computation-in-Memory (CIM) and Processing-near-Memory (PNM) architecture. Using RRAM as a main part of the system, a new computation hierarchy can be designed, in which analog RRAM array will serve as a CIM core for matrix-related computation and digital RRAM will serve as large-capacity distributed on-chip memory. At the current stage, digital RRAM technology is pretty mature, but analog RRAM technology still faces several major challenges, including device reliability degradation, accuracy loss, large AD/DA overhead, etc. In the future, system-technology co-optimization (STCO) is highly required for analog RRAM based CIM system to address the above challenges. On-chip training function will help to improve the computing accuracy and extend the application fields of analog RRAM based CIM chips. 1POPS computing power per chip and 20TOPS/W energy efficiency (whole SoC chip) on the RRAM chip for AI acceleration applications can be expected within 3 years